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The performance of 6.7 MFLOPS within the vector-matrix multiplication at 20 MHz has been attained by means of parallel operations. A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW energy consumption. Because the V60/V70 had been used for many Japanese arcade video games, MAME (for "Multiple Arcade Machine Emulator"), which emulates a number of outdated arcade video games for fanatics, includes an CPU simulator for their instruction set structure.

The structure integrates varied features into a single silicon die, such as a rich set of basic-purpose registers, high degree language oriented instruction set, floating-point knowledge dealing with which is suitable for scientific functions, and the FRM (Functionality Redundancy Monitoring) operation mode which supports highly-reliable programs configuration. Instruction codecs are suited to code-technology section of compilers.

This paper describes necessities for real-time UNIX operating techniques, design idea and the implementation of RX-UX 832 actual-time UNIX working system for v60/v70 microprocessor that are NEC's 32-bit microprocessors. A sophisticated 32-bit RISC microprocessor for embedded control; V810 is launched on this paper. The i486 microprocessor features a fastidiously tuned, 5-stage pipeline with an integrated 8-kB cache. In addition they permit the designers of a microprocessor to implement strategies used in the design of mainframe computers particularly with regard to pipeline structures.

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